1. Field of the Invention
The present invention relates to a device for addressing a memory, and in particular a dynamic memory. The device delivers address words each composed of first and second address words containing least significant bits and most significant bits of the address word. Generally speaking, the invention relates to sequential addressing of a memory such as that used in digital videocommunication systems where it is necessary to carry out inter-picture and/or infra-picture processing.
2. Description of the Prior Art
Memories generally offer a capacity of 4, 16, 64 or 256 Kbits, where the integer K is equal to 2.sup.10 =1024. Thus, for a 64-Kbit capacity memory, it is necessary to have address words with 6+10=16 bits in order to address the 1-bit cells of the memory. In order to limit the number of leads in a memory addressing-input bus and hence the number of pins on an integrated circuit package housing the memory, each 16-bit address word is split into two parallel 8-bit words transmitted in series. The first word contains the 8 least significant bits (LSB) of the address word and the second word contains 8 most significant bits (MSB) of the address word.
When the memory is of the alternate read and write addressing type, first and second read address words and first and second write address words are successively transmitted in an 8-lead addressing bus to the memory over one clock period defining an addressing cycle of a memory cell. In practice, the memory cells are arranged in a matrix of rows and columns. Each cell disposed at the intersection of a row and a column is addressed by a first 8-bit word indicating the number of the corresponding cell row and by a second 8-bit word indicating the number of the corresponding cell column.
As depicted schematically in FIG. 1, an addressing device for a 64-Kbit memory 5 comprises a 16-bit write counter 1 and a 16-bit read counter 2 simultaneously delivering a 16-bit write address word and a 16-bit read address word during each clock period respectively. The read and write address words are multiplexed in a 16-lead bus at an output from a multiplexer 3. The multiplexed 16-bit address words are then multiplexed into parallel 8-bit words in a second multiplexer 4 having an 8-lead output bus delivering first and second 8-bit read address words and first and second 8-bit write address words to eight addressing inputs of memory 5.
In integrated circuit technology based on TTL transistors for example, the addressing device shown in FIG. 1 requires four packages for each counter 1, 2, four packages for multiplexer 3 and two packages for multiplexer 4, i.e. fourteen integrated circuit packages in all.